1. Field
Example embodiments relate to methods that may store data bits of memory devices. Also, example embodiments relate to multi-level cell (MLC) memory devices or multi-bit cell (MBC) memory devices and/or data bit storage methods that may record/read data bits of the memory devices.
2. Description of Related Art
A multi-level cell (MLC) memory device that may store data of two or more bits in a single memory cell has been proposed in response to a need for higher integration of memory. The MLC memory device may also be referred to as a multi-bit cell (MBC) memory. However, as the number of bits programmed in the single memory cell increases, reliability may deteriorate and a read-failure rate may increase. To program ‘m’ bits in the single memory cell, any one of 2m threshold voltages may need to be generated in the memory cell. Threshold voltages of memory cells where the same data is programmed may generate a distribution within a predetermined range due to minute electrical characteristic differences between the memory cells. Each threshold voltage distribution may correspond to each of 2m data values generated by ‘m’ bits.
However, since a voltage window for a memory device is limited, a distance between 2m distributions of threshold voltages between adjacent bits may decrease as ‘m’ increases, and the distributions may overlap as the distance between the distributions decreases. When the distributions are overlapped, the read-failure rate may increase.
When data is stored over a long period of time, a lateral movement of a charge caused by an electrostatic attractive force between the charge stored in the memory cell and the charge stored in an adjacent cell may occur within a charge trap memory including a multi-level cell, thus leading to a higher probability that a read error occurs.